We gather and define the needs and expectations of project stakeholders. This process ensures that all essential requirements are identified and documented to guide the project’s development and success.

Requirements tracing in the ASIC design flow involves tracking and managing the requirements throughout the design process. This ensures that all design specifications are met from initial concept to final verification, maintaining alignment with the project’s goals and preventing deviations.

RTL Design does not involve coding. We generate a very detailed Micro-Architecture document and a Verification Procedures Document using the requirements document as a reference. In this design phase, we document the sub-block functional description, input and output interfaces of the top-level, and each sub-block’s connectivity and timing constraints, which are detailed in the Micro Architecture Document. Test cases, test procedures, test scenarios, and verification environments are defined, usually by a separate team of verification engineers, in the Verification Procedures Document.

Using the Micro-Architecture Document as a reference, engineers can start HDL coding using SystemVerilog/VHDL/Verilog to implement the design. Linting tools ensure that company HDL coding standards are followed. Static RTL Analysis is a well-accepted method in our daily work, and it helps us detect bugs.

RTL functional simulation is a critical step in the digital design process, where the behavior of the RTL code is verified to ensure it meets the design specifications. This simulation involves running test benches to validate the design’s functionality, checking for logical errors, and ensuring that the design performs as intended before moving on to synthesis and physical implementation.

Directed tests in digital IC design are a type of functional verification where specific test cases are developed to exercise particular features or functions of a digital design. These tests are based on the design requirements and intended behavior, ensuring the design performs as expected in predefined scenarios. Directed tests are often used in the early stages of verification to quickly identify bugs and validate the basic functionality of the design.

This step involves generating random input patterns to verify the functionality and robustness of a digital circuit. This method helps uncover unexpected issues and edge cases that might not be detected through directed tests, providing a more comprehensive verification of the design. Our team uses either SystemVerilog or VHDL-based random test case development techniques.

Assertion-based verification (ABV) is a technique used in digital IC design to ensure a design behaves correctly using assertions. Assertions are statements that describe expected conditions or behaviors within the design, and they must always hold true. ABV helps in identifying design errors early in the verification process by checking these conditions during simulation or formal verification.

RTL synthesis is a process in digital IC design where high-level RTL descriptions of a circuit are transformed into a gate-level representation. This involves converting the RTL code, typically written in hardware description languages like VHDL or Verilog, into a netlist that describes the circuit in terms of logic gates and interconnections. The synthesis process ensures that the design meets specified constraints such as timing, area, and power consumption and prepares the design for further stages like placement and routing.

DFT (Design for Testability) insertion in digital IC design involves adding specific test structures to a circuit to make it easier to test and debug. This process typically includes techniques like scan chains, built-in self-test (BIST), and boundary scan, which enhance the controllability and observability of internal nodes.

Static Timing Analysis (STA) is a method used in digital IC design to validate a circuit’s timing performance without requiring dynamic simulation. STA calculates the signal propagation delays along all possible paths in the design to ensure they meet timing constraints, such as setup and hold times.

This process helps ensure the circuit will operate correctly at the desired clock frequency, identifying potential timing violations that could affect performance.

FPGA prototyping helps in the early detection of design errors, facilitates hardware-software co-design, and accelerates time-to-market by enabling thorough testing and validation of the design under real-world conditions.