Analog IP Cores

PLL IP Core

Phase-Locked Loop analog IP core for clock synthesis, frequency multiplication, and jitter attenuation in mixed-signal designs.

TegraIC's PLL IP Core provides a fully characterized Phase-Locked Loop block for integration into mixed-signal ASICs and SoCs. Designed for technology portability, the PLL is optimized for low jitter, low phase noise, and minimal power consumption.

Features

Integer-N and fractional-N synthesis modes
Wide VCO frequency range
Low phase noise floor for RF and high-speed serial applications
Integrated loop filter options (on-chip or off-chip)
Lock detection output

Applications

Clock generation and distribution, frequency synthesis for RF transceivers, CDR (clock and data recovery), SerDes clock synthesis, and jitter attenuation in high-speed digital designs.

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