MIL-STD-1553 IP Core

The MIL-STD-1553 IP Core implements the MIL-STD-1553B standard and provides a single or multi-functional interface between the host processor and the MIL-STD-1553 bus transceiver.

Functional Modes

• Bus Controller (BC) — initiates and manages all data transfers on the bus
• Remote Terminal (RT) — supports two separate RT modes simultaneously
• Bus Monitor (BM) — passive monitoring of all bus traffic
• Multi-mode operation — BC, RT, and BM can operate simultaneously

Compliance

All avionic IP cores from TegraIC are DO-254 compliant, providing the design assurance required for airborne electronic hardware development and certification.

Integration

The core provides a standard AXI4-Lite host interface for straightforward integration into FPGA and ASIC designs. Complete documentation, integration guides, and simulation models are provided with the delivery package.