ARINC 429 IP Core

The ARINC 429 IP Core implements the ARINC 429 standard for avionics data bus communication. The IP core contains Rx and Tx processing blocks, a Controller Block, Internal Memory, and External Memory Interfaces.

Architecture

• Receive (Rx) Block — decodes ARINC 429 data words from the bus
• Transmit (Tx) Block — encodes and schedules ARINC 429 data words
• Controller Block — manages data flow between host and bus interfaces
• Internal Memory — on-chip buffer storage for data words
• External Memory Interface — optional extension for larger buffer requirements
• AXI Interface — standard AXI bus for CPU communication

Compliance

DO-254 compliant, suitable for incorporation into airborne electronic hardware programs.